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IR design, instruction selection, register allocation, and peephole optimization.
Common TAC Instructions
t1 = a + b // binary operation t2 = -a // unary operation t3 = a // copy t4 = a[i] // array load a[i] = t5 // array store t6 = &x // address-of t7 = *p // pointer load *p = t8 // pointer store if t9 goto L1 // conditional jump goto L2 // unconditional jump param t10; call f // function call t11 = call f // function with return
| Method | Complexity | Quality | Notes |
|---|---|---|---|
| Naive (stack only) | None | Poor | Every temp gets stack slot |
| Linear scan | O(n) | Good | Single pass; Poletto & Sarkar 1999 |
| Graph coloring | O(n²) | Best | Chaitin-Briggs; NP-complete in general |
| SSA-based | O(n log n) | Best | Leverages SSA form for coalescing |
Dataflow Equations
// GEN: variables used before defined in block
// KILL: variables defined in block
// IN[B] = USE[B] ∪ (OUT[B] - DEF[B])
// OUT[B] = ∪_{S∈succ(B)} IN[S]
// Live range: from definition to last use
// Interference graph: edge if ranges overlapmov r,r; mov r,r → single mov).